1. Field of the Invention
The present invention is related to a method of making an array of probes for use in probing electronic devices, such as a probe card for probing the dies on a semiconductor wafer.
2. Related Art
Semiconductor dies must be tested during the manufacturing process to insure the reliability and performance characteristics of integrated circuits on the dies. Accordingly, different testing procedures have been developed by semiconductor manufacturers for testing semiconductor dies. Standard tests for gross functionality are typically performed by probe testing the dies at the wafer level. Probe testing at the wafer level can also be used to rate the speed grades of the dies.
Testing a large number of integrated circuit chips in parallel at the wafer level provides significant advantage since test time and cost are substantially reduced. At present, large scale testers including mainframe computers are needed to test even one chip at a time, and the complexity of these machines is increased when the capability of testing arrays of chips in parallel is added. Nevertheless, because of the time savings parallel testing provides, high pin-count testers capable of probing and collecting data from many chips simultaneously have been introduced, and the number of chips that can be tested simultaneously has been gradually increasing.
Substantial lower cost would result from an improved wafer test and burn-in scheme that permits parallel test and burn-in of the chips on a wafer before dicing.
As wafer testing requirements become more sophisticated, the need for high density probes, and efficient and relatively inexpensive methods of manufacturing them continues to be a challenge. Accordingly, a need exists for an inexpensive and efficient method of manufacturing high density probe array.